1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacture thereof and, more particularly, to a technique to provide a semiconductor device having a high-speed device and a uniform plane bearing.
2. Description of the Prior Art
In integrated circuits in general, an epitaxially grown layer is grown on a silicon substrate, and circuits are then formed in the epitaxially grown layer. For example, an N type silicon substrate is first formed and then a P type epitaxially grown layer is grown thereon so as to allow desired circuits to be formed therein.
In such a structure, however, the silicon substrate and the epitaxially grown layer are so constructed as to join together, so that a pn junction is occurred in their interface area. The pn junction thus formed is such that it acts as capacitor and yields parasitic capacitance. As a result of the parasitic capacitance of the pn junction, an operating speed of the resulting device is made to reduce.
In the last few years, to solve this problem, a way of forming an additional silicon monocrystal layer to overlie the insulating layer on the silicon substrate (Semiconductor on Insulator, or SOI, technique) has been sought. This is to lay an insulating layer between the silicon substrate and the silicon monocrystal layer to thereby insulate them from each other and eliminate the pn junction. This SOI technique will be concretely described hereinbelow.
FIGS. 1A and 1B illustrates the conventional SOI technique using the ELO (Epitaxial Lateral Overgrowth) method as described in "Lateral Epitaxial Overgrowth of Silicon on SiO.sub.2," by D. D. Rathman et. al., JOURNAL OF ELECTRO-CHEMICAL SOCIETY SOLID-STATE SCIENCE AND TECHNOLOGY, October, 1982, p. 2303. In this ELO method, a silicon dioxide layer 41 which acts as insulating layer is grown on a semiconductor substrate 2, and thereafter subjected to etching using photoresist so as to open seed windows 61 (FIG. 1A).
Next, epitaxial growth of silicon is performed from the seed window 61 in the longitudinal direction, and subsequently in the lateral direction. By these processes, an epitaxial layer 81 is formed on the silicon dioxide layer 41 acting as insulating layer (FIG. 1B). In the obtained structure, the silicon dioxide layer 41 serves to reduces the interface area of the epitaxial layer 81 with the silicon substrate 2 down to the size of the seed window 61. Accordingly, the parasitic capacitance due to the pn junction is reduced, allowing high-speed operation of the device to be realized.
Another conventional method available is the SENTAXY method shown in FIGS. 1C and 1D ("New SOI-Selective Nucleation Epitaxy," by Ryudai Yonehara et. al., Preliminary Bulletin for the 48th Fall Academic Lecture 1987 by the Applied Physics Society, 19p-Q-15, p. 583). In this method, an insulating layer of silicon dioxide 42 is formed on a silicon substrate 2 and a plurality of silicon nuclei 82 for use in crystal growth are attached thereto (FIG. 1C). Here, silicon nuclei 82 are separately placed on the silicon dioxide layer 42.
Silicon nuclei 82 are then subjected to epitaxial growth (FIG. 1D). By using this method, the silicon substrate 2 and the epitaxial layer 83 can be fully isolated from one another by the existence of the dioxide layer 42. Accordingly, the pn junction is eliminated, allowing the parasitic capacitance to be avoided. Methods of forming the nuclei include formation of a small-area silicon nitride layer, or employment of the FIB (Focused Ion Beam) method.
However, the conventional SOI technique described above has the following disadvantages. First, in the ELO method shown in FIGS. 1A and 1B, the pn junction of the epitaxial layer 81 and the silicon substrate 2, although reduced to the size of the seed window 61 (FIG. 1B), is not fully eliminated. As a result, parasitic capacitance is allowed to generate to that extent and arrests further increase of the operating speed of the device.
Second, in the SENTAXY method shown in FIGS. 1C and 1D, the epitaxial layer 83 and the silicon substrate 2 are fully isolated from one another, thus overcoming the ELO method disadvantage. However, in the SENTAXY method, epitaxial growth is performed on the basis of silicon nuclei 82 which are placed on the silicon dioxide layer 42 and are not in contact with the silicon substrate 2.
Consequently, silicon substrate 2 and the epitaxial layer 83 are not formed connectively, and so, inconsistent in the plane bearing. In other words, the ELO method shown in FIGS. 1A and 1B allows the uniform plane bearing because the epitaxial layer is grown on the basis of the silicon substrate 2, whereas the SENTAXY method shown in FIGS. 1C and 1D gives inconsistent plane bearings. The differentiation in plane bearing is responsible for variation in oxidation rate, ion diffusion rate, and other characteristics, with the result that a device having desired electrical characteristics cannot be uniformly formed.